`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    11:15:59 03/10/2022 
// Design Name: 
// Module Name:    display 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module display(input [23:0]Data,
					input Clock,
					input Reset,
					output [5:0]Enable,
					output [3:0]Num,
					output En
					
    );
	 
	 reg [5:0]enable = 6'b0;
	 reg [5:0]fn =6'b0;
	 reg [3:0]num = 4'b0;
	 reg en;
	 reg[5:0]Switch=6'b111111;
	 
	 assign Num=num;
	 assign En=en;
	 
	 assign Enable = fn;
	 
	 always @(posedge Clock or posedge Reset)
	 begin
			if (Reset == 1'b1)
			begin
				enable <=6'b1;
			end 
			else 
			begin
				enable <=enable <<1;
				
				if (enable == 0)
				begin
					enable <=6'b1;
				end
				fn<=enable;
				
				if(enable == 6'b000001)
				begin
					en<=Switch[0];
					num<=Data[3:0];
				end
				else if (enable == 6'b000010)
				begin
					en<=Switch[1];
					num<=Data[7:4];
				end
				else if (enable == 6'b000100)
				begin
					en<=Switch[2];
					num<=Data[11:8];
				end
				else if (enable == 6'b001000)
				begin
					en<=Switch[3];
					num<=Data[15:12];
				end
				else if (enable == 6'b010000)
				begin
					en<=Switch[4];
					num<=Data[19:16];
				end
					else if (enable == 6'b100000)
				begin
					en<=Switch[5];
					num<=Data[23:20];
				end

									
			end
	 end
	 
	 
	 
	


endmodule
